Random access memory (RAM) is a ubiquitous component of modem digital architectures, RAM can be a standalone device, or can be integrated in a device that uses the RAM, such as a microprocessor, microcontroller, application specific integrated circuit (ASIC), system-on-chip (SoC), and other like devices. RAM can be volatile or non-volatile. Volatile RAM loses its stored information whenever power is removed. Non-volatile RAM can maintain its memory contents even when power is removed. Although non-volatile RAM has advantages, such as an ability to retain its contents without applied power, conventional non-volatile RAM has slower read/write times than volatile RAM.
Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology having response (read/write) times comparable to volatile memory. In contrast to conventional RAM technologies, which store data as electric charges or current flows, MRAM uses magnetic elements. As illustrated in FIGS. 1A and 1B, a magnetic tunnel junction (MTJ) storage element 100 can be formed from two magnetic layers 110 and 130, each of which can have a magnetic field, separated by an insulating (tunnel barrier) layer 120. One of the two layers (e.g., fixed layer 110), is pinned to a particular polarity. The other layer's (e.g., free layer 130) polarity 132 is free to change to match that of an external applied field. A change in the polarity 132 of the free layer 130 changes the resistance of the MTJ storage element 100. For example, when the polarities are aligned, as depicted in FIG. 1A, a low resistance state exists. When the polarities are not aligned, as depicted in FIG. 1B, then a high resistance state exists. The illustration of MTJ 100 is simplified, and each layer illustrated can comprise one or more layers of materials.
Referring to FIG. 2A, a memory cell 200 of a conventional MRAM is depicted during a read operation. The cell 200 includes a transistor 210, a bit line 220, a digit line 230 and a word line 240. The cell 200 is read by measuring the electrical resistance of the MTJ 100. For example, a particular MTJ 100 can be selected by activating an associated transistor 210, which can switch current from a bit line 220 through the MTJ 100. Due to a tunnel magnetoresistive effect, the electrical resistance of the MTJ 100 changes based on the orientation of the polarities in the two magnetic layers (e.g., 110, 130), as discussed above. A resistance inside any particular MTJ 100 can be determined from a current intensity determined by the polarity of the free layer. If the fixed layer 110 and free layer 130 have the same polarity, the resistance is low and a logic “0” is read. If the fixed layer 110 and free layer 130 have an opposing polarity, the resistance is higher and a logic “1” is read.
Referring to FIG. 2B, the memory cell 200 of a conventional MRAM is depicted during a write operation, which is a magnetic operation. Transistor 210 is off during the write operation. Current propagates through the bit line 220 and the digit line 230 to establish magnetic fields 250 and 260, which affect the polarity of the free layer of the MTJ 100, and consequently the logic state of the cell 200. Accordingly, data can be written to, and stored in, the MTJ 100.
MRAM has several desirable characteristics that make it a candidate for a universal memory, such as high speed, high density (i.e., small bitcell size), low power consumption, and no degradation over time.
A variation of MRAM is Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM). STT-MRAM uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter). STT-MRAM is also known as Spin Transfer Torque RAM (STT-RAM), Spin Torque Transfer Magnetization Switching RAM (Spin-RAM), and Spin Momentum Transfer (SMT-RAM). During a write operation, the spin-polarized electrons exert torque on a free layer, which switches a polarity of the free layer. During a read operation, a current detects the resistance/logic state of the MTJ storage element, as discussed in the foregoing description. As illustrated in FIG. 3A, a STT-MRAM bit cell 300 includes a MTJ 305, a transistor 310, a bit line 320, and a word line 330. The transistor 310 is switched on for both read and write operations to allow current to flow through the MTJ 305, so the logic state can be read or written.
Referring to FIG. 3B, a more detailed diagram of a STT-MRAM cell 301 is illustrated, for further discussion of the read/write operations. In addition to the previously discussed elements such as the MTJ 305, the transistor 310, the bit line 320 and the word line 330, a source line 340, a sense amplifier 350, read/write circuitry 360, and a bit line reference 370 are illustrated. As discussed above, the write operation in an STT-MRAM is electrical. The read/write circuitry 360 generates a write voltage between the bit line 320 and the source line 340. Depending on the polarity of the voltage between the bit line 320 and the source line 340, the polarity of the free layer of the MTJ 305 can be changed, and correspondingly, the logic state can be written to the cell 301. Likewise, during a read operation, a read current is generated, which flows between the bit line 320 and the source line 340 through the MTJ 305. When the current is permitted to flow via the transistor 310, the resistance (logic state) of the MTJ 305 is determined, based on the voltage differential between the bit line 320 and the source line 340, which is compared to a reference 370, and then amplified by the sense amplifier 350. Additional details are provided, for example, in U.S. Pat. No. 7,764,537, which is incorporated herein by reference in its entirety.
Accordingly, a non-volatile MRAM memory can be fabricated as an array of the memory cells 200. A gate of the transistor 210 is coupled to a word line (WL). During write operations, a supply voltage is applied to the bit line 220 or the digit line 230. During read operations, a read voltage is applied to the bit line 220, and the digit line 230 is set to ground. The WL is coupled to a supply voltage during both read and write operations.
Despite the characteristics described above, the memory cell 200 is not a perfect device. Sometimes, during either fabrication or use, the memory cells 200 in an MRAM memory can fail, which renders a non-volatile MRAM memory address having the failed memory cell 200 useless. In a conventional MRAM circuit, a programmable read-only memory (PROM) stores the failed address in an antifuse array, to prevent the failed memory cell 200 from storing data.
There are long-felt industry needs for apparatus and methods to reduce a size of a device storing the failed memory cell's addresses. Reducing the size of the failed address storage device will improve performance, and reduce size, of a device into which the MRAM is integrated. There are also long-felt industry needs for apparatus and methods to reduce the number of interconnects used to access the device storing the failed memory cell's addresses, as well as to increase the number of stored repair cell addresses.